Memory implemented error detection and correction code with addr

Details Memory implemented error detection and correction code with addr Memory implemented error detection and correction code with addr

1997-03-25

1998-05-12

Beausoliel, Jr., Robert W.

Excavating

371 492, G11C 2900

Patent

active

057517452

ABSTRACT:
A method and apparatus for performing digital signal error detection through the use of a string of received incoming system address bits. The incoming address bits are divided into groups according to whether they contain a high value of "1" or a low value of "0". At least one address parity bit is then generated from each group and used in checking the integrity of data received.

REFERENCES:
patent: 3531631 (1970-09-01), Burgess
patent: 3555255 (1971-01-01), Tay et al.
patent: 4443876 (1984-04-01), Ng
patent: 4747106 (1988-05-01), Wakimoto

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