Excavating
Patent
1991-09-19
1994-08-09
Beausoliel, Jr., Robert W.
Excavating
371 51, G06F 1100
Patent
active
053373189
ABSTRACT:
A testing apparatus for a memory IC with a redundancy circuit includes a first memory, a counter, a second memory and a comparator. The first memory has a memory area for row addresses or column addresses of a target memory with a redundancy circuit, and stores row addresses or column addresses of defective bits of the target memory. The counter counts the number of defective-bit containing rows or columns of the target memory. The second memory stores a number of rows or columns of spare memory cells provided in the redundancy circuit. The comparator compares a count value of the counter with the number stored in the second memory. When the count value of the counter exceeds the number of rows or columns of spare memory cells stored in the second memory, it is considered unrepairable and test is terminated. When the former value does not exceed the latter, memory cells in a defective-bit containing row or column in the target memory are replaced with memory cells in an associated row or column in the redundancy circuit based on the row addresses or column addresses stored in the first memory.
REFERENCES:
patent: 4339657 (1982-07-01), Larson et al.
patent: 4414665 (1983-11-01), Kimura et al.
patent: 5224101 (1993-06-01), Popyack, Jr.
Shirasaka Hisatoshi
Tsukakoshi Hisao
Beausoliel, Jr. Robert W.
Chung Phung My
Kabushiki Kaisha Toshiba
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