Static information storage and retrieval – Interconnection arrangements
Patent
1992-07-17
1994-09-06
LaRoche, Eugene R.
Static information storage and retrieval
Interconnection arrangements
365 52, 257686, 257696, G11C 506
Patent
active
053454120
ABSTRACT:
A memory IC includes a memory element having a chip select signal input terminal and a decoder for decoding a portion of an address input signal to output, from the decoding, a chip select signal from one of a plurality of output terminals. One of the plurality of output terminals is connected to the chip select signal input terminal of said memory element for selecting the memory element for read and write operations. A memory device includes a plurality of memory ICs, each having a memory element, a decoder for decoding a portion of an address input signal to output, from the decoding, a chip select signal from one of a plurality of output terminals, and a plurality of leads connected to the memory element and the decoder. One of the plurality of output terminals is connected to the chip select signal input terminal of the memory element for selecting the memory element for read and write operations. The specific output terminals of the decoders of the respective memory ICs differ from each other.
REFERENCES:
patent: 4398235 (1983-08-01), Lutz et al.
patent: 4884237 (1989-11-01), Mueller et al.
LaRoche Eugene R.
Mitsubishi Denki & Kabushiki Kaisha
Tran Andrew Q.
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