Memory having selected state on power-up

Details Memory having selected state on power-up Memory having selected state on power-up

1988-12-20

1991-05-21

Fears, Terrell W.

Static information storage and retrieval

Read only systems

With override

365154, G11C 1300

Patent

active

050181025

ABSTRACT:
A memory cell which includes a pair of cross-coupled CMOS inverters. Each inverter has a capacitor coupled from its output to either the supply voltage or ground potential. One inverter has a capacitor coupled from its output to a voltage supply terminal and the other inverter has a capacitor coupled from its output to a ground terminal. Upon the application of power to the memory cell, the output of each inverter of the pair assumes a predetermined logic state thereby preventing dc current flow in either side of the cross coupled pair. In addition to providing for reduced power consumption, the selective cell assymetry provided makes possible a random access memory device that stores a fixed program at power up.

REFERENCES:
patent: 4224686 (1980-09-01), Aneshansley

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