Memory having P-type split gate memory cells and method of...

Details Memory having P-type split gate memory cells and method of... Memory having P-type split gate memory cells and method of...

2011-06-07

2011-06-07

Luu, Pho M (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185120, C365S185280, C365S185290

Reexamination Certificate

active

07957190

ABSTRACT:
A memory comprising a plurality of P-channel split-gate memory cells are organized in rows and columns. Each of the plurality of P-channel split-gate memory cells comprises a select gate, a control gate, a source region, a drain region, a channel region, and a charge storage layer comprising nanocrystals. Programming a memory cell of the plurality of P-channel split-gate memory cells comprises injecting electrons from a channel region of the memory cell to the charge storage layer. Erasing the memory cell comprises injecting holes from the channel region to the charge storage region.

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Lee et al; “NeoFlash—True Logic Single Poly Flash Memory Technology”; 2006 Non-Volatile Semiconductor Memory Workshop, IEEE, pp. 15-16.

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