Memory having distributed reference and bias voltages

Details Memory having distributed reference and bias voltages Memory having distributed reference and bias voltages

1992-05-08

1994-03-01

LaRoche, Eugene A.

Static information storage and retrieval

Powering

365 63, G11C 514

Patent

active

052914550

ABSTRACT:
A memory (20) has N.sub.BIAS generators (63 and 73) coupled to the positive and negative power supply lines (61 and 62) at a point close to amplifiers (84 and 85) and address buffers (76) to insure that they all receive the same power supply voltage to prevent an impact on the access times of memory (20). A V.sub.CS generator (65) is located close to power supply bonding pads (23 and 25) and to output buffers (77 and 78) to reduce the effects of power supply line noise on the noise margins. A V.sub.AREF generator provides a reference voltage to the differential amplifiers of address buffers (75 and 76). Locating V.sub.AREF generator (67) close to power supply bonding pads (23 and 25) insures that the reference voltage is always at the midpoint of the input logic swing.

REFERENCES:
patent: 4906863 (1990-03-01), Van Tran
patent: 5001362 (1991-03-01), Tran
Blood, William R. Jr., "MECL System Design Handbook", Fourth Edition, 1988, pp. 93-101.

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