Memory having and method for providing a reduced access time

Details Memory having and method for providing a reduced access time Memory having and method for providing a reduced access time

1995-08-28

1998-04-28

Yoo, Do Hyun

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

36518905, 365193, 365194, 36523006, 365236, G11C 800

Patent

active

057454299

ABSTRACT:
A memory device includes an array of memory cells that are arranged in row and columns. A row latch receives a row address and a latch signal and stores the row address in response to a transition of the latch signal. A row decoder is coupled between the latch and the array. In response to a transition of a row address strobe, which occurs a first predetermined time after the transition of the latch signal, the row decoder fires a row of the memory cells that are identified by the row address.

REFERENCES:
patent: 5287237 (1994-02-01), Takasugi

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