Memory having a plurality of external clock signal inputs

Details Memory having a plurality of external clock signal inputs Memory having a plurality of external clock signal inputs

1997-10-29

1999-03-23

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

365194, G11C 800

Patent

active

058869484

ABSTRACT:
A method and apparatus for operating a synchronous memory from a plurality of external clock signals is described. By providing external system, read, and write clock signals, a memory is operated by delaying operational clock signals, such as read and write clock signals, with respect to a system clock signal in order to reduce the apparent access time of the synchronous memory and/or to increase setup time to the synchronous memory. The delay of the read and write clock signals with respect to the system clock signal may be accomplished through a phase-lock-loop or delay-lock-loop which is off-chip with respect to the integrated circuit synchronous memory. Delay circuitry may be employed for operating one or more than one synchronous memories.

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patent: 5663661 (1997-09-01), Dillon et al.

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