Memory for programmable digital filter

Details Memory for programmable digital filter Memory for programmable digital filter

1993-02-23

2001-11-06

Mai, Tan V. (Department: 2787)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reissue Patent

active

RE037440

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a memory for programmable digital filter for wide-band electronic signals, particularly video signals.
PRIOR ART
More particularly the invention relates to an EPROM memory which can be used to implement a digital filter of the non-recursive type with finite impulse response (FIR) of the kind described in
the antedated patent application No. 22890-A/88

U.S. Pat. No.
5
,
103
,
416

in the name of the same Applicant, entitled “Programmable Digital Filter”, filed on
Dec. 6, 1988

Nov.
21
,
1989
.
Said antedated patent relates to a digital filter of the kind with a transposed canonical structure, wherein an array of multipliers provides partial products of the digital signal to be filtered by successive coefficients of the filter's impulse response. The antedated patent replaces said multipliers with tables of pre-calculated partial products contained in one or more re-programmable memories, and each memory cell contains the partial product of an associated stage which corresponds to the value to be processed which coincides with the address of said cell. In particular, said antedated patent uses a single memory which contains, in each line, all the partial products between the address of that line and all the coefficients from h
0
, to h
T
, T being the overall number of coefficients of the filter. The line is transmitted in parallel to the arithmetical block of the filter by means of a bank of read amplifiers which are equal in number to the length of the memory line.
However, though the use of a table thus defined instead of multipliers offers advantages in terms of operating speed, simplicity of implementation etc., as the precision of the coefficients of the filter rises, the dimensions of the memory also grow in a linear manner together with the number of read amplifiers, with an increase in silicon area occupation and with a consequent limitation of the performance obtainable from a filter integrated according to a given technology.
SUMMARY OF THE INVENTION
The aim of the invention is to provide a programmable digital filter which has the tabular memory architecture described in said antedated patent application, which requires a smaller memory capacity than said prior filter for an equal equivalent output dynamics and with no complications in the circuits associated with the memory. In a typical application, a digital filter according to the present invention provides in output an equivalent dynamics of 20 word bits with a memory size which would allow a dynamics of only 16 bits in said antedated patent application.
Together with the reduction in memory size and therefore in the occupied silicon area, the invention also provides an increase in the filter's processing speed (as required, for example, for video applications) for an equal dynamics, or an increase in dynamics with unchanged speed.
The invention achieves the above mentioned aim and other objects and advantages such as will become apparent from the continuation of the description with a programmable digital filter which comprises an arithmetical chain of parallel adders alternated with delay elements, and a memory constituted by a plurality of lines of a plurality of one-bit cells, each being addressable by a decoder controlled by a digital signal to be filtered, each memory line containing side by side values corresponding to the partial products of successive impulse response coefficients for a value equal to the line address, said memory furthermore comprising a number of read amplifiers which is equal to the number of cells of one line in order to read the bits of the addressed line, the outputs of said amplifiers being connected to respective parallel inputs of the adders of said arithmetical chain, characterized in that each memory line contains said values in two's-complement binary form in words which decrease in length by one bit for each increment of 2 in the characteristic of said coefficients, starting from the one with lowest characteristic, and in that the output of each read amplifier corresponding to the most significant bit of each value is connected to the corresponding input bit line of the associated adder and to all the other most significant input bit lines.


REFERENCES:
patent: 4709343 (1987-11-01), Van Cang
patent: 4809205 (1989-02-01), Freeman
patent: 4811262 (1989-03-01), White
patent: 5103416 (1992-04-01), Cavallotti et al.

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