Memory error logger which sorts transient errors from solid erro

Details Memory error logger which sorts transient errors from solid erro Memory error logger which sorts transient errors from solid erro

1977-12-02

1980-06-24

Shaw, Gareth D.

Boots, shoes, and leggings

371 38, G06F 1100

Patent

active

042098467

ABSTRACT:
A method of and an apparatus for distinguishing between transient and solid errors within a single-error-correcting semiconductor memory storage unit (MSU) comprised of a plurality of large scale integrated (LSI) bit planes and for notifying the associated data processing system of required maintenance action. The method utilizes an error logging store (ELS) that is comprised of a plurality of memory error registers one for each separately associated word group within the MSU. Each memory error register contains storage for: (1) the Error Correction Code (ECC) defined, failing bit position; (2) the single bit error counter; (3) the multiple single bit error tag; and (4) the multiple bit error tag. Upon detection of an error within a word group, the associated memory error register is accessed to determine the history of previously detected errors within that word group. The central processing unit (CPU) is notified by a priority interrupt of the error status of that word group if:

REFERENCES:
patent: 3045779 (1977-08-01), Markle
patent: 3704363 (1972-11-01), Salmassy et al.
patent: 3999051 (1976-12-01), Petschauer

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