Memory error correction system distributed on a high performance

Details Memory error correction system distributed on a high performance Memory error correction system distributed on a high performance

1989-12-22

1992-09-08

Baker, Stephen M.

Excavating

G06F 1110

Patent

active

051464616

ABSTRACT:
A distributed error correction circuit for a synchronous high performance multiprocessor bus wherein the memory directly transfers data containing error fields to the multiprocessor bus without performing an error check. Each device, such as a plurality of processors or input/output busses, connected to the multiprocessor bus has error correction circuitry located between the multiprocessor bus and the device to perform error correction while the data is being transferred off the multiprocessor bus and stored in data buffers at the bandwidth of the multiprocessor bus. The error correction circuit detects and corrects data errors caused by the memory or the multiprocessor bus. The stored data is later transferred out of the buffers at the bandwidth of the device. Data from a device is delivered into the device buffers at the bandwidth of the device for later delivery of the data into memory at the bandwidth of the multiprocessor bus. During such transfers, the error correction circuitry generates the error field as the device data is transferred onto the multiprocessor bus.

REFERENCES:
patent: 4085448 (1978-04-01), Kogge
patent: 4468731 (1984-08-01), Johnson et al.
patent: 4633472 (1986-12-01), Krol
patent: 4723244 (1988-02-01), Iacoponi
patent: 4791641 (1988-12-01), Hillis
patent: 4811361 (1989-03-01), Bacou et al.
patent: 4965883 (1990-10-01), Kirby
patent: 4995041 (1991-02-01), Hetherington et al.
Lin, S., et al., Error Control Coding, copyright 1983 by Prentice-Hall, Inc., N.J., pp. 111-113.
Pryce, D., "Fiber-optic ICs accelerate communication over data links", EDN, Jun. 9, 1988, pp. 63-72.
Grover, W., "Forward Error Correction in Dispersion-Limited Lightwave Systems", IEEE J. Lightwave Technology, vol. 6, No. 5, May 1988, pp. 643-654.
Tate, G., et al., "EDC chip boosts memory reliability", Electronic Design, Sep. 1, 1980, pp. 151-155.
Twaddell, W., "Error-checking and -correcting ICs see wider use as memory size grows", EDN, Mar. 4, 1981, pp. 31-40.
No author, "Bus ECC for High Availability and Recovery in Real Time", IBM Technical Disclosure Bulletin, vol. 32, No. 5B, Oct. 1980, pp. 235-236.
Rao, T., et al., Error-Control Coding for Computer Systems, copyright 1989, pub. by Prentice-Hall, Inc., pp. 138-143.

Affiliated with

Also associated with

Rating

Memory error correction system distributed on a high performance does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory error correction system distributed on a high performance, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory error correction system distributed on a high performance will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-139886