Memory employing separate dynamic reference areas

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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Details

C365S185210, C365S210100, C365S210140

Reexamination Certificate

active

07940570

ABSTRACT:
A memory that employs separate Dynamic reference (Dref) areas to provide a threshold voltage reference signal. The memory includes the separate Dref areas, a data area positioned between the Dref areas, a reference array, and one or more sense amplifiers. The data area is arranged to provide an output signal, the reference cell and the separate Dref areas are arranged to provide the threshold voltage reference signal, and the sense amplifiers are arranged to receive the output signal and the threshold voltage reference signal.

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patent: 7808830 (2010-10-01), Kasuta
patent: 2004/0208074 (2004-10-01), Schnabel et al.
patent: 2007/0291550 (2007-12-01), Yang et al.
patent: 2008/0144388 (2008-06-01), Yamashita
patent: 2004110881 (2004-04-01), None

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