Memory employing redundant cell array of multi-bit cells

Details Memory employing redundant cell array of multi-bit cells Memory employing redundant cell array of multi-bit cells

2008-12-05

2011-12-06

Luu, Pho M. (Department: 2824)

Static information storage and retrieval

Floating gate

Multiple values

C365S185090, C365S185200, C365S185290

Reexamination Certificate

active

08072802

ABSTRACT:
A memory that employs a redundant cell array for recovery of one or more failed core cell arrays of multi-bit memory cells is described. The memory includes a plurality of core cell arrays, at least one redundant cell array, and a memory controller. The memory controller is configured to dynamically assign the redundant cell array to a failed core cell array when erasing at least a portion of the plurality of core cell arrays. The memory controller is further configured to provide read/write access to the redundant cell array when the failed core cell array is selected for read/write access.

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