Memory employing independent dynamic reference areas

Details Memory employing independent dynamic reference areas Memory employing independent dynamic reference areas

2011-06-14

2011-06-14

Mai, Son L (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185210, C365S210100, C365S210140

Reexamination Certificate

active

07961519

ABSTRACT:
A memory that employs separate Dref areas that are independently accessed to provide a threshold voltage reference signal. The memory includes the separate Dref areas, a data area positioned between the Dref areas, one or more sense amplifiers, and a switch component. The switch component is arranged to receive addressing data and to independently couple one of the separate Dref areas to the sense amplifiers based, at least in part, on a physical proximity of individual memory cells along a word line.

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patent: 2004/0208074 (2004-10-01), Schnabel et al.
patent: 2007/0291550 (2007-12-01), Yang et al.
patent: 2008/0144388 (2008-06-01), Yamashita
patent: 2004110881 (2004-04-01), None

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