Memory efficient topological converter assembly

Details Memory efficient topological converter assembly Memory efficient topological converter assembly

1992-06-05

1993-11-16

Canney, Vincent P.

Excavating

36523001, G06F 1100

Patent

active

052630293

ABSTRACT:
A memory testing assembly (50) for testing a memory device under test ("DUT") includes a row address converter (58) and a column address converter (62). The row and column address converters translate generic row and column count signals into correct row and column address signals that address desired memory cells in a particular DUT. The row and column address converters comprise separate memory arrays, which allow them to employ a relatively small amount of memory bits. The row and column address converters are, however, cross-coupled to provide row and column information signals that are fed back to inputs of the respective column and row address converters. Such feedback allows the memory tester to be able to test DUTs for which some of the row addresses must be known to translate the column addresses and/or some of the column addresses be known to translate the row address. The memory tester writes data into the cells of the DUT and reads and compares the read data with the previously written data. The memory tester includes a data pattern generator (74) that controls the data topology of the data written into cells of the DUT.

REFERENCES:
patent: 4757503 (1988-07-01), Hayes et al.
patent: 5157664 (1992-10-01), Waite

Affiliated with

Also associated with

Rating

Memory efficient topological converter assembly does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory efficient topological converter assembly, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory efficient topological converter assembly will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-27048