Memory efficient channel decoding circuitry

Details Memory efficient channel decoding circuitry Memory efficient channel decoding circuitry

1997-03-24

1999-08-31

Pham, Chi H.

Multiplex communications

Generalized orthogonal or special mathematical techniques

Fourier transform

370203, 375219, 375260, 375232, 36472602, 36472603, H04B 138, H04L 516

Patent

active

059462930

ABSTRACT:
A memory efficient channel decoder circuit is provided for channel decoding differentially modulated data samples comprising multiple adjacent carriers each including two data samples associated therewith. The decoder circuit includes a pair of working read/write memory circuits partitioned into even and odd memory blocks, a separate read/write memory circuit connected thereto, and a complexmultiplier circuit having a first input connected to the working memory circuits, and a second input coupled to the separate read/write memory and a read only memory containing predefined calculation values. An in-place decimation-in-time FFT algorithm is used to differentially demodulate and frequency descramble (de-interleave) the data samples of each data symbol, as well as providing for automatic frequency control correction of the data samples.

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