Memory devices using tri-state buffers to discharge data...

Details Memory devices using tri-state buffers to discharge data... Memory devices using tri-state buffers to discharge data...

2007-08-07

2007-08-07

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S185250, C365S189050, C365S204000

Reexamination Certificate

active

11153508

ABSTRACT:
A memory device includes a sense amplifier circuit, a tri-state buffer, a data latch circuit and a data line. The sense amplifier circuit senses and amplifies a current of a memory cell. The tri-state buffer receives an output of the sense amplifier circuit. The data latch circuit latches an output of the tri-state buffer. The data line connects the tri-state buffer and the data latch circuit. The memory device removes charge on the data line using a latch enable signal, which is applied to the tri-state buffer before a read operation.

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patent: 9-73779 (1997-03-01), None
patent: 2003-338190 (2003-11-01), None

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