Static information storage and retrieval – Addressing – Counting
Reexamination Certificate
2000-06-06
2001-04-24
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Counting
C365S230050, C365S230030, C365S221000
Reexamination Certificate
active
06222793
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit devices, and more particularly to memory devices.
BACKGROUND OF THE INVENTION
Memory devices typically store (write) and retrieve (read) data from a memory array based on an address. In conventional memory devices, such as the synchronous dual port memory device
10
illustrated in
FIG. 1
, the address utilized for a read or write operation may be either an external address or an internally generated count which originates at a loaded address or a zero address. As is seen in
FIG. 1
, the dual port memory device
10
includes a memory array
12
, I/O controls
14
and
14
′, input latches
18
and
18
′, drivers
20
and
20
′, read/write control latches
22
and
22
′, and NOR gates
24
and
24
′ which control the drivers
20
and
20
′ to activate during read operations, AND gates
26
and
26
′ which provide a read/write control signal to the I/O controls
14
and
14
′, chip enable control gates
28
and
28
′ and chip enable latches
30
and
30
′.
Also provided are counter/address registers
16
and
16
′. The counter/address registers
16
and
16
′ latch the address on the external address bus of the device for read and write operations and provide this address to the memory array
12
. The counter/address registers
16
and
16
′ also provide an internally generated count to the memory array as an address. The count may be reset to 0 by the {overscore (CNTRST)} signal and started by the signal {overscore (CNTEN)}. The memory array
12
may then be sequentially accessed, beginning with an externally loaded address or 0 by incrementing the count.
FIG. 2
illustrates a possible circuit to carry out the functions of the counter/address registers
16
and
16
′. As seen in
FIG. 2
, a multiplexer
32
receives the external address A
0
-A
15
as one input. The multiplexer
32
is controlled by the {overscore (ADS)} signal so that when {overscore (ADS)} is active, the multiplexer
32
outputs the external address. A second multiplexer
34
receives the output of the first multiplexer
32
and outputs either the output of the first multiplexer
32
or all 0's based on the signal {overscore (CNTRST)}. If {overscore (CNTRST)} is active, then all 0's are output and if {overscore (CNTRST)} is inactive, then the output of the second multiplexer
34
is the output of the first multiplexer
32
. The output of the second multiplexer
34
is provided to a counter/register
36
which stores the output of the multiplexer
34
on each cycle of CLK. The output of the counter/register
36
is provided to the memory array
12
and also provided to an adder
38
and a third multiplexer
40
. The adder
38
increments the address value output by the counter/register
36
by
1
and provides that value to the third multiplexer
40
. The third multiplexer
40
provides its output to the first multiplexer
32
. The output of the third multiplexer
40
is controlled by the signal {overscore (CNTEN)} to output the value of the counter/register
36
if {overscore (CNTEN)} is inactive and the incremented value of the counter/register
36
if {overscore (CNTEN)} is active.
A truth table for the address counter control is illustrated in Table 1.
TABLE 1
Address Counter Control
Pre-
Ad-
vious
dress
Address
CLK
{overscore (ADS)}
{overscore (CNTEN)}
{overscore (CNTRST)}
I/O
MODE
X
X
↑
H
H
L
Dout
Counter reset
(0)
to Address 0
An
X
↑
L
H
H
Dout
External
(n)
Address
Utilized
X
An
↑
H
H
H
Dout
External
(n)
Address
Blocked -
Counter
disabled
X
An
↑
H
L
H
Dout
Counter
(n+1)
Enabled -
Internal
Address
generation
As is seen in the above truth table and from the circuit illustrated in
FIG. 2
, the address may be reset to Address 0 but may not be reset to an externally loaded address. To restart a read or a write operation which utilized internal address generation at an address other than 0, a new address is loaded from the external address bus. Accordingly, an additional address cycle may be required to restart any non-zero operations. Thus, if a write operation is immediately followed by a read or a series of read operations from the same initial non-zero or intermediate starting address, the initial starting address will be loaded for each operation. Additional dual port memory devices having a loadable address for read operations are illustrated in U.S. Pat. No. 4,633,441.
In other devices, such as first-in-first-out (FIFO) buffers, internal addresses may be utilized to access memory. These pointers to memory may be utilized to track the sequence in which data is stored in memory to create a FIFO from a random access memory. In particular in FIFOs with a “fast retransmit mode,” a read address may be stored and used as a mark to return to begin transmission. Typically, this read address does not correspond to an external address and the FIFO typically reads to this address and then sets a mark to begin retransmission. An example of such a FIFO is illustrated in U.S. Pat. No. 5,365,485.
SUMMARY OF THE INVENTION
Embodiments of the present invention may provide methods of controlling a memory device and memory devices including a memory array having an internal address input which specifies a location in the memory array accessed during read operations and write operations. An external address input receives an address value from a device external to the memory device. The received address value may be utilized to randomly access the memory array. An address register/restart address counter is operatively associated with the memory array and the external address input and configured to store a start address for at least a write operation to the memory array, to selectively generate a series of internal addresses to access the memory array based on the stored start address and to selectively return to the stored start address as a start address of a subsequent operation to access the memory array.
In particular embodiments of the present invention, the address register/restart address counter includes a register operatively connected to the external address input and configured to selectively store address values received at the external address input. A loadable counter having an input operatively associated with the register and the external address input so as to allow the selective loading of address values received by the external address input and address values stored in the register and having an output operatively associated with the memory device so as to provide the internal address values to the memory array may also be included. A counter restart input is operatively associated with the loadable counter so as to load the counter with an address value stored in the register when the counter restart input is active.
In still further embodiments of the present invention, a counter enable input is operatively associated with the loadable counter. The loadable counter may then be configured to increment from the loaded address value when the counter enable input is active. In particular embodiments, the register may also be configured to store each address value received on the external address input as a start address for at least a write memory operation. Preferably, however, the register is configured to store each address value received on the external address input as a start address irrespective of whether a memory operation is a read memory operation or a write memory operation.
In still further embodiments of the present invention, the loadable counter is configured to be restarted to the address stored in the register by the counter restart input without receiving an address value on the external address input so as to perform a memory operation utilizing the stored address value and without receiving an external address. In such embodiments, the address value stored in the register may be a start address value of a write memory operation and the memory operation performed utilizing the stored address
Intergrated Device Technology, Inc.
Lam David
Myers Bigel Sibley & Sajovec P.A.
Nelms David
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