Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2006-09-05
2006-09-05
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185170, C365S185230, C365S185330, C365S185290
Reexamination Certificate
active
07102927
ABSTRACT:
Methods are provided to program a memory device having a plurality of memory blocks. A first address for selecting a row of each of the memory blocks is generated according to a multi-page program operation. A second address for selecting a memory block is received and latched, which is repeated until second addresses of memory blocks to be selected are all received and latched. Memory blocks are selected by the latched second addresses, and then the same rows of the respective selected memory blocks are simultaneously activated according to the first address. Related memory devices also are described.
REFERENCES:
patent: 5299162 (1994-03-01), Kim et al.
patent: 5473563 (1995-12-01), Suh et al.
patent: 5696717 (1997-12-01), Koh
patent: 5841721 (1998-11-01), Kwon et al.
patent: 5999446 (1999-12-01), Harari et al.
patent: 6493037 (2002-12-01), Raiyat
patent: 6507885 (2003-01-01), Lakhani et al.
patent: 6587915 (2003-07-01), Kim
patent: 6587925 (2003-07-01), Arimilli et al.
patent: 2002/0099903 (2002-07-01), Lakhani et al.
patent: 2004/0172576 (2004-09-01), Yoshii et al.
patent: 2003-109384 (2003-04-01), None
Myers Bigel & Sibley & Sajovec
Tran Andrew Q.
LandOfFree
Memory devices and programming methods that simultaneously... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory devices and programming methods that simultaneously..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory devices and programming methods that simultaneously... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3535785