Memory device with variable trim setting

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S185240

Reexamination Certificate

active

07826265

ABSTRACT:
A memory device includes a memory array including a plurality of cells. The cells are divided into a plurality of subsets. Each subset has at least one associated trim parameter. The trim parameter for each subset is stored in the memory array within the associated subset. Circuitry is operable to program at least a portion of a selected subset using the associated trim parameter. A method for operating a memory device includes storing at least one trim parameter for each of a plurality of subsets of a memory array in the memory device within each of the subsets. At least a portion of a selected subset is programmed based on the at least one trim parameter associated with the selected subset.

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patent: 7160284 (2007-01-01), Ullestad et al.
patent: 7463520 (2008-12-01), Aritome
patent: 2003/0031056 (2003-02-01), Roohparvar
patent: 2005/0122831 (2005-06-01), Roohparvar
patent: 2006/0015691 (2006-01-01), Louie et al.
patent: 2006/0256620 (2006-11-01), Nguyen et al.
patent: 2007/0047315 (2007-03-01), Aritome
patent: 2007/0223278 (2007-09-01), Aritome

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