Memory device with time shared data lines

Details Memory device with time shared data lines Memory device with time shared data lines

2000-09-01

2002-09-03

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S233100

Reexamination Certificate

active

06445641

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates in general to semiconductor memories and in particular to a memory device that allows I/O buses to be shared between data and control information.
For certain electronic applications, memory devices provide the capability of simultaneously writing large blocks of data. An example is the use of random access memory (RAM) circuitry in graphics applications. A video graphics system typically uses a RAM to store data that represent the color or intensity of light for every picture cell (pixel) on the video screen. Frequently, adjacent pixel groups display exactly the same information within a graphic output, such as a screen display. To decrease the number of write cycles required to fill the memory with such data, the video RAM is capable of writing the same data simultaneously in multiple adjacent column addresses. This function is commonly referred to as a “block write” operation. A graphics memory device, such as a RAM, typically includes color registers which store write data during block write operations. A block write operation may involve writing, for example, 16 columns at a time wherein address bits A<7:4> are decoded for addressing column cells and bits A<3:0> are disregarded according to industry standards.
Also, some graphics applications support what is called “masking functions.” Such functions can occur during a normal write operation (i.e., write per bit mode) whereby individual masked bits permit memory locations to keep their original data, even if addressed for writing. Masking operations performed during block write can mask one or more entire columns. A single masking bit that masks a certain column is referred to as a “column mask bit.” The column mask bits (“CMBs”) are supplied through the data I/O (“DQ”) pins and are typically decoded by the column decoder similar to normal column address bits.
Architecturally, a memory device, such as a RAM circuit, is typically arranged in several identical memory arrays with each array including a matrix of memory cells located at intersections of a number of columns, or bit lines, (“BLs”) and rows, or word lines (“WLs”). A 256 Meg dynamic RAM (DRAM), for example, may be divided into four banks, with each bank divided into two blocks and each block made up of 32 memory arrays, each array including 2 Megs of memory cells located at intersections of 1024 bit line pairs and 512 word lines.
FIG. 1
shows a simplified example of a layout architecture for a memory block. Cell array
100
corresponds, for example, to a block of memory that is made up of multiple smaller arrays
110
. Block
102
, which includes data I/O pads (“DQ” pads) as well as data input buffers, is typically placed at one end of the array. Another block
104
includes I/O sense amplifiers and write drivers. In graphics DRAMs, block
104
may also include color registers for holding block write data where such registers are usually disposed between the DQ pads/input buffers and the cell array. Column redundancy circuitry
112
for replacing defective memory cells, and column decoder
106
, are typically placed on the other side of array
100
with I/O buses
108
extending vertically across the array.
This type of memory organization, which is commonly found in memory devices, creates layout inefficiencies in certain applications. For example, column mask bits (CMBs) which are supplied by the data input buffers in block
102
must traverse cell array
100
to reach the column redundancy and column decoder
106
. This creates some layout difficulties and increases the array size, and thus the overall size and cost of the memory device.
SUMMARY OF THE INVENTION
The present invention provides methodology and circuitry for time sharing existing interconnects, such as I/O buses, that traverse the cell array to carry both data as well as control information, such as column mask bits. This results in a more compact layout for the memory device which in turn provides for a more cost effective implementation.
According to one embodiment, the present invention includes a memory device having an array of memory cells distributed in rows and columns. Further, a plurality of interconnects extend across the array and are coupled together to carry write data and control data during a first and a second period of time, respectively. In a specific embodiment, the control data includes column mask information for block write operations.
In another embodiment, the present invention includes a method of operating a memory device in block write mode. The process has the steps of receiving column mask information on input nodes located at one end of an array of memory cells and then driving the column mask information onto array-long interconnect lines. The column mask information is received by circuitry across the array of memory cells during a first period of time. Next, write data is driven onto the interconnect lines to supply write data to the memory array cells during a second period of time. The second time period is different than the first time period. For example, column mask bits which prevent certain graphical information from changing on a screen, are driven onto an I/O bus during time, t
1
. During another time period, t
2
, color write data for coloring non-masked cells is driven onto the same I/O bus. Thus, a single I/O bus is used with the above time-sharing methodology to multiplex column mask and color write information to provide a more cost effective implementation..
The following detailed description and drawings provide a better understanding of the nature and advantages of the memory device with time-shared I/O lines according to the present invention.


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