Memory device with support for unaligned access

Details Memory device with support for unaligned access Memory device with support for unaligned access

2000-02-18

2001-07-03

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Addressing

Multiplexing

C365S230010, C365S230030, C365S230060, C365S189020

Reexamination Certificate

active

06256253

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a memory device with support for unaligned access. Such a memory may be incorporated in a microprocessor or microcontroller. In particular, modern microprocessors or microcontrollers provide the capability of loading and storing multiple words in parallel. Therefore, the memory unit is designed to input and output multiple words. For example, a memory unit has a
128
bit wide bus to read and write four 32-bit words in parallel. In particular, if a memory system is integrated with a microprocessor or microcontroller, for example as a cache sub-system, this allows extremely high data throughput.
FIG. 9
shows such an arrangement according to the prior art. The memory unit consists of four memory blocks
1
,
2
,
3
, and
4
. Each memory block
1
,
2
,
3
, and
4
provides a 32-bit wide interface which is connected to an alignment unit
6
. A select logic unit
5
is provided which receives an address from terminal from a central processing unit (not shown). If an address provided to terminal
7
has a start address within the memory unit which begins at memory block
1
, an aligned access to the memory unit takes place. A 128-bit word consisting of the content of memory cells M
1
, M
2
, M
3
, and M
4
will be fed to the aligner
6
which connects this output directly to terminal
8
. In case of an unaligned access to the memory unit the following scenario takes place. If, for example, an address provided at terminal
7
starts within the memory unit at memory block
3
, the 128-Bit word consists of the content of memory cells M
3
, M
4
, M
5
, and M
6
. Only the first two 32-bit words M
3
and M
4
can be accessed in a first cycle because the system can only access one memory line during one cycle. In other words, only memory line M
1
, M
2
, M
3
, and M
4
or memory line M
5
, M
6
, M
7
, and M
8
can be accessed during one cycle. In this example, the requested 128-bit word is distributed over two different memory lines. During a second cycle, the remaining two 32-bit words M
5
and M
6
will be retrieved from memory block
1
and
2
and merged in a register. Aligner
6
multiplexes the output of memory blocks
1
,
2
,
3
, and
4
to output the aligned 128-bit word at terminal
8
in the correct order, namely M
3
, M
4
, M
5
, and M
6
.
A major disadvantage of this arrangement is the above-described “one cycle penalty” due to the structure of the memory unit in case of an unaligned access as well as a timing disadvantage. Time critical programming can therefore not support any unaligned memory access.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a memory system which allows unaligned access with a minimal time delay, for example, within a single cycle. This object is achieved by an integrated memory comprising a plurality of data lines and a plurality of decoders being associated to each data line. Each data line can address a single memory cell or a plurality of memory cells. Also, each data line can be either a word line or a bit line of a memory. Each decoder generates an enable signal upon receiving of its associated address signal. A plurality of multiplexers having two inputs and an output associated to each data line are provided. The enable signal of each decoder is supplied to a first input of the associated multiplexer and to a second input of the multiplexer associated to the next higher addressed data line, and a control input for controlling said multiplexers.
In another embodiment a memory system comprises m memory banks. Each memory bank has an n-bit input/output interface, wherein each of at least m−1 memory banks comprise a plurality of data lines and a plurality of decoders being associated to each data line. Each data line can address a single memory cell or a plurality of memory cells. Also, each data line can be either a word line or a bit line of a memory. Each decoder generates an enable signal upon receiving of its associated address signal. A plurality of multiplexers having two inputs and an output associated to each data line are provided, wherein the enable signal of each decoder is supplied to a first input of the associated multiplexer and to a second input of the multiplexer associated to the next higher addressed data line. A control input for controlling the multiplexers is provided.
In yet another embodiment a memory unit comprises a plurality of word lines and a plurality of bit lines arranged in a matrix, wherein each cross point comprises a memory cell. A plurality of word line decoders having a decoder output associated to each word line and a plurality of multiplexers each comprising two inputs and an output associated with each word line are provided, wherein each multiplexer is coupled with the output of its associated decoder and with the output of the decoder for the next lower addressed word line. The output of the multiplexers controls each associated word line and the multiplexers are controlled by a select signal.


REFERENCES:
patent: 5973950 (1999-10-01), Shindo
patent: 6021084 (2000-02-01), McLaury
patent: 6047352 (2000-04-01), Lakhani et al.
patent: 6061291 (2000-05-01), Zheng
patent: 6072735 (2000-06-01), Komoriya et al.
patent: 6118720 (2000-09-01), Heile
patent: 6122218 (2000-09-01), Kang
patent: 6122219 (2000-09-01), Zheng et al.
patent: 6130854 (2000-10-01), Gould et al.

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