Memory device with standby function

Details Memory device with standby function Memory device with standby function

1991-05-22

1993-05-04

Sikes, William L.

Static information storage and retrieval

Addressing

36523006, 365227, 365236, G11C 802

Patent

active

052087816

ABSTRACT:
A memory device includes a memory, an address latch, a built-in incrementer, and an address decoder. The address decoder has a mapping register which assigns the memory to a predetermined address. The address decoder further includes a standby signal producer which detects whether or not the address latch addresses an address specified by the mapping register and which sets the memory device to a standby state of a low power consumption when such is not detected. The memory device can be set to a standby state even when the memory device is connected to a microcomputer with a protocol by which an address of the memory is not outputted each time. This arrangement enables to save power consumption of the computer, to decrease the load of a power supply circuit in a microcomputer applied apparatus and to make the apparatus compact.

REFERENCES:
patent: 4561070 (1985-12-01), Armstrong
"Low Power Decoding Scheme for Partitioned Arrays" IBM Tech Disc. Bul. vol. 29 No. 4, Sep. 1986 1533-1535.

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