Memory device with reduced power consumption

Details Memory device with reduced power consumption Memory device with reduced power consumption

1999-12-13

2000-10-24

Mai, Son

Static information storage and retrieval

Powering

Conservation of power

36523008, G11C 700

Patent

active

061377449

ABSTRACT:
A memory device, such as a SDRAM, has an active mode and a standby mode. A memory core is controlled in the active state and the standby state. First and second latch circuits respectively latch a data signal and a command signal, when clocked. In the active state, a buffer circuit connected to the first latch circuit, latches the latched data signal, and generates a buffered data signal. A register is connected to the buffer and receives and stores the buffered data signal. A decision circuit, connected between the second latch circuit and the buffer circuit, decodes the latched command signal and selectively activates the buffer circuit based on the decoded command. In the standby mode, the latched data signal is not provided to the buffer circuit. Power may also not be provided to the buffer circuit in the standby mode.

REFERENCES:
patent: 5300831 (1994-04-01), Pham et al.
patent: 5812000 (1998-09-01), Kobayashi et al.
patent: 5889709 (1999-03-01), Fukuda
patent: 5973529 (1999-10-01), Chappell et al.

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