Memory device with reduced operating voltage having...

Details Memory device with reduced operating voltage having... Memory device with reduced operating voltage having...

2005-03-15

2005-03-15

Auduong, Gene N. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S185330

Reexamination Certificate

active

06868014

ABSTRACT:
A non-volatile memory device includes a semiconductor substrate and a pair of buried bitlines within the substrate. A scaled down dielectric stack is formed over the substrate. The scaled down dielectric stack includes a scaled down top dielectric layer, a scaled down charge trapping dielectric layer and a bottom dielectric layer. A wordline is formed over the dielectric stack. The memory device is operative to be programmed using a reduced wordline operating voltage of less than about +8 Volts, and to be erased using a reduced wordline operating voltage of less than about −6 Volts.

REFERENCES:
patent: 3992701 (1976-11-01), Abbas et al.
patent: 6011725 (2000-01-01), Eitan
patent: 6215702 (2001-04-01), Derhacobian et al.
patent: 6434053 (2002-08-01), Fujiwara

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