Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2008-03-25
2008-03-25
Mai, Son L. (Department: 2827)
Static information storage and retrieval
Interconnection arrangements
C365S051000, C365S189020, C365S230030
Reexamination Certificate
active
11388464
ABSTRACT:
In some embodiments, a chip includes at least four groups of memory banks and at least four groups of output conductors wherein each group of output conductors corresponds to a different one of the groups of memory banks. The chip also includes circuitry to perform a read operation by providing read data from at least one of the banks of each of the groups of memory banks to its corresponding group of output conductors. Other embodiments are described.
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Bains Kuljit S.
Halbert John
Aldous Alan K.
Intel Corporation
Mai Son L.
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