Memory device with rapid word line switch

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

Reexamination Certificate

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Details

C365S230030, C365S200000

Reexamination Certificate

active

11132635

ABSTRACT:
A memory device includes an array of storage cells, multiple words lines, where each word line corresponds to a row in the array of storage cells, and multiple bit lines, where each bit line corresponds to a column in the array of storage cells. The device further includes a row decoder attached to the multiple word lines. The row decoder is operable to assert and to de-assert individual word lines. Each of the word lines has a head portion adjacent to where the word line is attached to the row decoder. The memory device supports a column decode sequence for accessing multiple storage cells within a row of the array. The column decode sequence both commences and terminates at or near the head portion of the word line corresponding to the row.

REFERENCES:
patent: 6650568 (2003-11-01), Iijima
patent: 7006397 (2006-02-01), Toda
patent: 2003/0210583 (2003-11-01), Yiu et al.
patent: 2004/0003195 (2004-01-01), Takahashi et al.

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