Memory device with pulse circuit for timing data output, and met

Details Memory device with pulse circuit for timing data output, and met Memory device with pulse circuit for timing data output, and met

1993-05-19

1994-09-20

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Sync/clocking

36518905, 365191, 365193, G11C 700

Patent

active

053495667

ABSTRACT:
A memory device includes an output buffer for temporarily storing first and second data that are sequentially retrieved from a memory array during a read cycle. The output buffer holds the first data until it is replaced by the second data. A pulse circuit is connected to the memory array and output buffer, and is designed to generate a pulse signal as soon as data becomes valid. The pulse signal causes the output buffer to replace the first data with the second data and to latch the second data therein until receipt of the next data. The pulse circuit generates the data valid signal upon receipt of the column address strobe and the presence of data on the data I/O lines. A method for outputting data from the memory device is also described.

REFERENCES:
patent: 4701889 (1987-10-01), Ando
patent: 4872143 (1989-10-01), Sumi
patent: 4947379 (1990-08-01), Okuyama
patent: 5014245 (1991-05-01), Muroka
patent: 5058066 (1991-10-01), Yu
patent: 5111386 (1992-05-01), Fujishima
patent: 5200926 (1993-04-01), Iwahashi

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