Memory device with interconnected polysilicon layers and method

Details Memory device with interconnected polysilicon layers and method Memory device with interconnected polysilicon layers and method

1985-11-07

1987-11-10

Edlow, Martin H.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 41, 357 59, 365185, H01L 2978, H01L 2702, H01L 2904, G11C 1134

Patent

active

047061022

ABSTRACT:
A memory device, based upon a field effect transistor having a floating gate is constructed for use in a silicon integrated circuit array of similar memory devices. The memory device includes only two polysilicon layers, a portion of each polysilicon layer being connected to each other through a via hole in an intervening silicon dioxide layer to form the floating gate.

REFERENCES:
patent: 4099196 (1978-07-01), Simko
patent: 4274012 (1981-06-01), Simko
patent: 4300212 (1981-10-01), Simko
patent: 4314265 (1982-02-01), Simko
patent: 4404577 (1983-09-01), Cranford, Jr. et al.
patent: 4422092 (1983-12-01), Guterman
patent: 4486769 (1984-12-01), Simko
patent: 4495693 (1985-01-01), Iwahashi et al.

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