Memory device with increased data throughput

Details Memory device with increased data throughput Memory device with increased data throughput

2006-02-28

2006-02-28

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189050

Reexamination Certificate

active

07006404

ABSTRACT:
A memory device (200) can include memory cell arrays (202-aand202-b) accessed according to phase shifted clock signals. Memory cell array (202-a) can be accessed at double data rates essentially synchronous with clock signal CLK. Memory cell array (202-b) can be accessed at double data rates essentially synchronous with a phase delayed clock signal DCLK. Such an arrangement can provide eight data accesses (four reads and four writes) in a single clock cycle.

REFERENCES:
patent: 5657292 (1997-08-01), McClure
patent: 6728157 (2004-04-01), Yagishita et al.
Cypress Data Sheet: 18-Mb QDR-II SRAM 2-Word Burst Architecture, Jan. 23, 2004.

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