Memory device with improved output operation margin

Details Memory device with improved output operation margin Memory device with improved output operation margin

2006-01-17

2006-01-17

Ho, Hoai (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189050, C365S193000, C365S194000

Reexamination Certificate

active

06987705

ABSTRACT:
A synchronous memory device which generates a data output enable signal corresponding to a set CAS latency mode including: a control clock generator for generating an A-type first control clock and a B-type first control clock; a first redundancy enable signal generator for shifting an internal read signal by a predetermined interval in synchronization with one of the A-type first control clock and the B-type first control clock and generating a plurality of first redundancy enable signals; a second redundancy enable signal generator for synchronizing the plurality of first redundancy enable signals with a DLL clock and generating a plurality of second redundancy enable signals; and an output enable signal generator for selecting one redundancy enable signal corresponding to the set CAS latency mode among the first redundancy enable signals and the second redundancy enable signals and generating the selected redundancy enable signal as the data output enable signal.

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