Memory device with dummy cell transistor

Details Memory device with dummy cell transistor Memory device with dummy cell transistor

1999-03-19

2000-03-14

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

3651852, 36518521, 3651851, 36518518, 36518525, G11C 1606

Patent

active

060381728

ABSTRACT:
A non-volatile semiconductor memory device including a memory cell transistor, a bit line connected to the memory cell transistor, a current controlling element connected between the bit line and a first potential, a dummy cell transistor connected between the bit line and a second potential, and a decoder connected to the memory cell transistor and the dummy cell transistor. The memory cell transistor has an electrically isolated floating gate electrode which varies an on resistance that depends on an amount of charge stored on the floating gate electrode. The decoder, which controls the memory cell transistor and the dummy cell transistor, is operative during a first interval to turn the dummy cell transistor on to apply the second potential to the bit line which is connected to the first potential via said current controlling element and it is operative during a second interval to turn the memory cell transistor on to allow the second potential to be applied to the bit line via the memory cell transistor, thereby allowing a write-in current to pass via the memory cell transistor.

REFERENCES:
patent: 5563826 (1996-10-01), Pascucci et al.
patent: 5699295 (1997-12-01), Yero
patent: 5805500 (1998-09-01), Campardo

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