Static information storage and retrieval – Powering
Reexamination Certificate
1999-12-06
2001-10-23
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Powering
C365S227000, C365S228000
Reexamination Certificate
active
06307802
ABSTRACT:
TECHNICAL FIELD
This invention relates in general to memory devices, and in particular to memory devices with voltage regulators.
BACKGROUND OF THE INVENTION
Modern memory devices, such as dynamic random access memories (DRAMs), often include an internal voltage regulator to derive a regulated internal supply voltage from an external supply voltage. This internal supply voltage is typically provided to the memory device's memory cell array and to the array's peripheral control circuits on a common power bus.
This typical voltage regulation system can be problematic for three reasons. First, the common power bus can be very long in a modern memory device. As a result, localized variations in the internal supply voltage along the bus can go unregulated by the internal voltage regulator. Second, sudden current draws from the common power bus by the memory cell array at the beginning of active cycles of the memory device can produce noise in the internal supply voltage which can affect operation of the array's peripheral control circuits. Third, the typical internal voltage regulator uses power relatively inefficiently.
Therefore, there is a need in the art for a memory device with a voltage regulation system which provides responsive regulation of the internal supply voltage along the entire length of the power bus. The system should also reduce the effect noise from the memory cell array has on operation of the array's peripheral control circuits, and it should use power more efficiently.
SUMMARY OF THE INVENTION
The present invention provides a memory device comprising a memory cell array, a plurality of control circuits operatively coupled to the array, and a voltage regulation system. The system includes an array power bus operatively coupled to the array for distributing an array supply voltage to the array, and a control circuit power bus operatively coupled to the plurality of control circuits for distributing a control circuit supply voltage to the plurality of control circuits. The system also includes a first regulator circuit operatively coupled to, for example, the array power bus at a first location along the array power bus for providing and regulating the array supply voltage. The system further includes a second regulator circuit operatively coupled to, for example, the control circuit power bus at a first location along the control circuit power bus for providing and regulating the control circuit supply voltage. Finally, the system includes a third regulator circuit operatively coupled to, for example, the control circuit power bus at a second location spaced apart from the first along the control circuit power bus for providing and regulating the control circuit supply voltage. The second location is far enough from the first location along the control circuit power bus to allow the third regulator circuit to respond to a localized variation in the control circuit supply voltage at the second location.
Preferably, the regulator circuits are constructed such that they can be turned on and off in response to control signals received from the control circuits. Also, the control circuits are preferably operatively coupled to the first, second and third regulator circuits for providing the control signals in a variety of operating modes of the memory device. The control signals turn on only the regulator circuits required for each operating mode during active cycles of the memory device and turn the regulator circuits off during stand-by cycles of the memory device.
The present invention thus provides a memory device with a voltage regulation system which provides responsive regulation of, for example, the control circuit supply voltage along the entire length of the control circuit power bus. The system also reduces the effect noise from the memory cell array has on operation of the array's control circuits by providing separate array and control circuit power busses. Finally, the system is more efficient with power because only the regulator circuits required for each operating mode of the memory device are turned on during active cycles of the memory device.
REFERENCES:
patent: 4855613 (1989-08-01), Yamada et al.
patent: 5046052 (1991-09-01), Miyaji et al.
patent: 5293334 (1994-03-01), Shimizu
patent: 5307318 (1994-04-01), Nemoto
patent: 5335203 (1994-08-01), Ishii et al.
patent: 5574697 (1996-11-01), Manning
patent: 5818780 (1998-10-01), Manning
patent: 6009034 (1999-12-01), Manning
Dorsey & Whitney LLP
Le Vu A.
Micro)n Technology, Inc.
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