Memory device with decoder having simplified structure

Details Memory device with decoder having simplified structure Memory device with decoder having simplified structure

1999-07-30

2000-11-21

Nelms, David

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523003, G11C 800

Patent

active

061512672

ABSTRACT:
A semiconductor memory device include a memory cell plate and a plurality of decoders. The memory cell plate includes a plurality of memory cells arranged in a matrix of rows and columns. Each of the plurality of decoders includes a series connection of at least two MOS transistors. One of two nodes of the series connection is connected to a state signal which is associated with one of the columns, and which is not activated in an active mode. Also, gate control signals are generated by predecoding a part of an address signal and supplied to gates of the at least two MOS transistors, respectively, whereby one of the rows is selected based on a potential of the other node of the series connection. The state signal may be a bit line precharge signal.

REFERENCES:
patent: 5668485 (1997-09-01), Rountree
patent: 5970016 (1999-10-01), Ohsawa
patent: 6021087 (2000-02-01), Bosshart
Itoh, "Super LSI Memory", Nov. 1994, Baihuukan, pp. 152-153 and p. 378.

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