Memory device with a plurality of common data buses

Details Memory device with a plurality of common data buses Memory device with a plurality of common data buses

2000-10-25

2001-12-25

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S063000, C365S230010, C365S233100

Reexamination Certificate

active

06333890

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory device such as a DRAM, and more particularly to a memory device having common data buses for a plurality of banks, to speedup the readout operations.
2. Description of the Related Art
Attention is being paid to synchronous dynamic RAMs (SDRAMS, FCRAMs (fast cycle RAMS), etc.) as high-speed dynamic RAMS. To further speed up data read, in such a dynamic RAM, the data read is performed through bank interleaving. The bank interleaving is a data read approach for reading data in a time-shared manner from a plurality of banks obtained as a result of segmentation of a memory area.
FIG. 1
is a configuration diagram of a memory device having a conventional bank configuration. The memory device shown in
FIG. 1
has a memory area which is segmented into four banks Bank
0
to Bank
3
, each provided with a plurality of memory cells, a word decoder, a column decoder, a sense amplifiers, etc.
The banks Bank
0
to Bank
3
are connected to global data buses GDB
0
to GDB
3
corresponding thereto, which in turn are connected via common data bus switching circuits CDBSW
0
to CDBSW
3
to a common data bus CDB shared by the four banks. The common data bus switching circuits CDBSW
0
to CDBSW
3
each include a transfer gate Trasf.A
0
consisting of an N-type transistor and a P-type transistor that are connected to each other in parallel.
The output of the common data bus CDB is connected via a latched circuit
11
to a transfer gate Trsf.A
1
which in turn is connected via a latched circuit
15
to a data input/output terminal DQ.
The synchronous memory device performs data read and write in synchronism with a clock signal. In order to read, after reading data from a bank, the next data from the same bank, however, the bank configured memory device has to stand by for at least the duration corresponding to the time from read of first data to the completion of read preparation for the next data, i.e., corresponding to the minimum operation cycle time tRC (RAS cycle time) of the sense amplifier. In case of tRC=3×tCLK memory device (tCLK is a clock cycle), for example, READ commands can be issued every third clock at most to read data from the same bank.
For this reason, with the memory area of the memory device segmented into a plurality of banks, the memory device data read operation can be sped up by effecting the bank interleaving for reading, for the duration when data are not to be read from a bank, data from another bank. This applies equally to the case of data write.
FIG. 2
is a timing chart obtained when the data are read by bank interleaving in the conventional memory device shown in FIG.
1
. The memory device operates in synchronism with a clock signal CLK having a cycle tCLK, and the banks are fed with read commands RD
0
, RD
1
, etc in synchronism with the rise of the clock signal CLK. In case of successive feed of read commands RD
0
to the same bank, e.g., the bank Bank
0
, the period equal to the minimum operation cycle tRC needs to be provided between the two commands RD
0
.
The banks provide respective data as their outputs to the global data buses GDB
0
, GDB
1
, etc., in response to read commands RD
0
, RD
1
, etc., and feed the respective data to the common data bus CDB in synchronism with the rise of a gate signal A
0
from the transfer gate Trsf.A
0
. In this case, the cycle of the gate signal A
0
from the transfer gate Trsf.A
0
is equal to the cycle of the clock signal CLK so that the data of the common data bus CDB vary every cycle tCLK of the clock signal CLK.
Data output to the common data bus CDB are held in the latched circuit
11
and, in synchronism with the rise of a gate signal A
1
of the transfer gate Trsf.A
1
, held in the latched circuit
15
. The data held in the latched circuit
15
are then fed to the input/output terminal DQ.
In this manner, the conventional memory device is able to read each bank data into the common data bus CDB by bank interleaving, to feed the data to the input/output terminal DQ at the cycle tCLK equal to that of the clock signal CLK. The reverse operation is performed in case of data write into each bank.
When the conventional memory device thus reads data of a plurality of banks by interleaving and feeds the data to the input/output terminal DQ, the common data bus CDB iterates the level transition between the low and high levels at the cycle tCLK of the clock signal CLK.
In the event of highly integrated, e.g., 128-Mbit or 256-Mbit memory devices, however, the common data bus CDB tends to have an elongated in-chip wiring and therefore an increased wiring capacity. This results in an elongated rise and fall time of data read into the common data bus CDB, whereupon the thus read data may not correctly reach the input/output terminal DQ with the operation clock CLK in a high-frequency band.
On the contrary, provision of the common data bus on each of the plurality of banks enables the level transition cycles of the respective common data buses CDB to be delayed, so that the read data can correctly reach the input/output terminal DQ. As a result, however, the number of common data buses CDB comes up to
(the number of banks) ×(the number of input/output terminals)
in the entire memory device, thus increasing the memory device chip area.
SUMMARY OF THE INVENTION
It is therefore the object of the present invention to provide a memory device capable of bank interleaving at a high-speed frequency band with use of as small a number of common data buses as possible.
According to an aspect of the present invention, in order to attain the above object, a memory device having a plurality of banks carries out bank interleaving by use of a plurality of common data buses, the number of which is less than the number of the banks. The present invention enables the data to be read more rapidly while suppressing the increase of the chip area.
According to another aspect of the present invention, in order to achieve the above object, there is provided a memory device having a plurality of banks each including a plurality of memory cells, and reading or writing data from or into the memory cells in synchronism with a clock signal, the memory device comprising: a plurality of common data buses shared by the plurality of banks, the number of the common data buses being less than the number of the banks; and switching circuits disposed on each of the plurality of banks, for feeding or receiving data of the each bank to or from the plurality of common data buses; wherein read or write of data of the plurality of banks is made through successive selection of the plurality of common data buses by the switching circuit.
According to the present invention, output or input of each bank data is made through the successive selection of the plurality of common data buses, whereby it is possible to delay the level transition cycle in a single common data bus. For this reason, the common data bus data can correctly be transmitted to the input/output terminal DQ even in case the common data bus has a large wiring capacity with elongated rise or fall time of level of the common data bus in the bank interleaving at a high-frequency band.
It is also possible to reduce the number of common data buses in the entire memory device by
(n−m)×(the number of input/output terminals)
as compared with the case of provision of common data buses on a bank-to-bank basis, which will contribute to a higher integration of the memory device. (n: number of banks, m: number of data buses)
In a preferred form of the present invention, the number of the common data buses is equal to the number of commands provided in the minimum operation cycle of the sense amplifier.
According to the present invention, (the number of the common data buses×tCLK) is equal to the sense amplifier minimum operation cycle, with the result that the data transition interval of the common data buses becomes equal to the minimum operation cycle so that each bank data can most effectiv

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