Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-12-08
2003-06-03
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185280, C365S185290, C257S315000
Reexamination Certificate
active
06574143
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to memory devices and has particular but not exclusive application to flash memory devices.
BACKGROUND OF THE INVENTION
Attention is being directed to finding a high-capacity storage medium to replace the disk drive in computing applications. The storage medium should not have any moving parts, should have comparable capacity and have equivalent, if not better, access time as compared with the disk drives currently available. One possible candidate as a replacement is non-volatile memory based on flash memory.
A flash memory cell is an electrically erasable and programmable, non-volatile memory device and an overview of this field is given in “Flash Memory Cells—An Overview” by Pavan et al., pp. 1248-1271, Proceedings of the IEEE, Vol 85, No. 8 (1997).
A flash memory cell is based on a floating gate transistor design in which a floating gate is separated from a channel by a tunnel oxide. The cell is programmed and erased by electrons tunnelling on and off the floating gate through the tunnel oxide.
To retain charge stored on the floating gate, the tunnel oxide is relatively thick, As a result it takes a long time, of the order of 100&mgr;s, to program and erase the cell. Furthermore, to permit electrons to tunnel on and off the floating gate, a large bias is applied across the barrier.
During program cycles, tunnelling from the channel to the floating gate is helped by the fact that electrons are “heated” as they pass along the channel and by the fact that the effective height of the tunnel barrier is reduced by band-bending at the interface of the channel and the tunnel barrier. The net result of these processes is that electrons meet the tunnel barrier as hot electrons and the tunnel current is considerably increased.
A hot electron is an electron that is not in thermal equilibrium with the lattice and has an energy several times k
b
T above the Fermi energy, where k
b
is Boltzmann constant and T is lattice temperature in degrees Kelvin.
On the other hand, during erase cycles, electrons tunnelling from the floating gate do not benefit from these processes and electron transport through the tunnel barrier is by Fowler-Nordheim tunnelling only. Consequently, a higher bias is required to erase information. Furthermore, Fowler-Nordheim tunnel currents are lower than hot-electron tunnel currents and so erasing takes longer than programming Thus, the erasing cycle limits the speed of operation of the cell.
The present invention seeks to solve the problems of high operating bias and slow operation.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention there is provided a memory device comprising a path for charge carriers, source and drain regions disposed at either end of the path, a node for storing charge carriers to produce a field which alters the conductivity of the path and first and second converters each for converting stored charge carriers into hot charge carriers so as to allow said charge carriers to leave said node and enter said source or drain regions in response to a given voltage configuration and for preventing charge carriers entering said source and drain regions in the absence of said voltage configuration.
The device may further comprise a control electrode operable to control charging and discharging of the node. The first converter may comprises a hot-charge diode, such as a hot-electron diode.
The first converter may comprise semiconductor material, such; as silicon, and may be undoped or doped with an impurity. The impurity concentration may be less than 10
17
cm
−3
.
The impurity may comprise an element that donates electrons, such as phosphorous or arsenic or and an element that accepts electrons, such as boron.
The device may further comprise a first tunnel barrier through which charge carrier may tunnel to reach the node and the first converter may comprise a second tunnel barrier. The first and second tunnel barriers may be unitary.
The second converter may comprise a third tunnel barrier and the first barrier, second and third tunnel barriers can be unitary.
The unitary tunnel barrier can be of a uniform thickness and may comprise silicon dioxide, silicon nitride or silicon oxynitride. The thickness of the unitary tunnel barrier may be between 2 and 10 nm.
Said charge carriers may enter the node via the first tunnel barrier and leave the node via the second or third tunnel barrier,
The first tunnel barrier may be disposed between said node and said path. Charge carriers may pass onto said node in response to a different voltage configuration. The device may comprise a first runnel barrier through which charge carrier may tunnel to reach the node.
The first converter may comprises a diffusion barrier which may comprise silicon nitride and be 0.5 to 3 nm thick. The converter and the node may be unitary.
According to a second aspect of the present invention there is provided a memory device comprising a path for charge carriers, a node for storing charge carriers to produce a field which alters the conductivity of the path and a converter for converting stored charge carriers into hot charge carriers so as to allow said charge carriers to leave said node and enter said source or drain regions in response to a given voltage configuration and configured to prevent charge carriers form leaving said not in the absence of said voltage configuration.
According to a third aspect of the present invention there is provided a memory device comprising a channel for charge carriers, a node for strong charge carriers to produce a field which alters the conductivity of the channel, a tunnel barrier disposed between said node and said path for preventing charge carriers from entering or leaving said node, the improvement comprising a hot charge diode for additionally preventing charge from tunnelling from said channel to said node and said tunnel barrier being sufficiently thin to allow said node to We both charged and discharged on a sub microsecond timescale.
The tunnel barrier may be sufficiently thin to allow said node to: be both charged and discharged in approximately 100 ns.
According to a fifth aspect of the present invention there is provided a memory device comprising a channel for charge carriers, a node for storing charge carriers to produce a field which alters the conductivity of the channel, a tunnel barrier disposed between said node and said path for preventing charge carriers from entering or leaving said node, the improvement comprising a hot charge diode for additionally preventing charge from tunnelling from said channel to said node and said tunnel barrier having a thickness between 2 to 10 nm.
Said tunnel barrier may be approximately 4 nm thick and comprise silicon dioxide
According to a sixth aspect of the present invention there is provided a method of operating a memory device comprising applying a gate bias to the control electrode, a drain bias to the drain region and a source bias to the source region. The applying of the gate bias may comprise setting the gate bias to 0V and setting either the drain bias or the source bias to 6V.
According to a seventh aspect of the present invention there is provided a method of fabricating a memory device comprising defining a path for charge carriers, defining source and drain regions disposed at either end of the path, providing a node for storing charge carriers to produce a field which alters the conductivity of the path and providing first and second converters each for converting stored charge carriers into hot charge carriers so as to allow said charge carriers to leave said node and enter said source or drain regions in response to a given voltage configuration and for preventing charge carriers entering said source and drain regions in the absence of said voltage configuration.
According to a eighth aspect of the present invention there is provided a method of fabricating a memory device, the method comprising providing a substrate, depositing a plurality of layers on said substrate, selectively etching at le
Hitachi Europe, Ltd.
Ho Hoai
Kenyon & Kenyon
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