Memory device, use thereof and method for synchronizing a...

Static information storage and retrieval – Addressing – Sync/clocking

Reexamination Certificate

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Details

C365S189020, C365S221000, C713S400000

Reexamination Certificate

active

07420869

ABSTRACT:
The invention includes a memory device with a register device to which an output of a multiplexer is connected. The input of the multiplexer is connected to a buffer store. In addition, the memory device includes a synchronization circuit having a control output connected to a control input of the multiplexer. A clock signal output of the synchronization circuit is connected to the clock input of the register device. The synchronization circuit generates and outputs a clock signal to the clock signal output derived from a time profile for a signal on a state input and from a signal on a second clock input. In this way, a data word to be stored in the register device is synchronized to a clock signal on the second clock input, so that data errors are avoided during transfer.

REFERENCES:
patent: 4965794 (1990-10-01), Smith
patent: 6104770 (2000-08-01), Yama
patent: 6338127 (2002-01-01), Manning
patent: 6662304 (2003-12-01), Keeth et al.
patent: 2001/0021142 (2001-09-01), Ooishi
patent: 10 2004 043 520 (2006-03-01), None

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