Memory device preventing a slow operation through a mask signal

Details Memory device preventing a slow operation through a mask signal Memory device preventing a slow operation through a mask signal

1998-10-05

2000-06-06

Nelms, David

Static information storage and retrieval

Addressing

Byte or page addressing

36518901, 36523003, G11C 800

Patent

active

060727497

ABSTRACT:
This invention is a memory device with a structure that has eliminated the logic circuit using I/O mask signal DQM from within the critical path from the clock CLK to the predecoder and column decoder for generating column selection signal CL. The logic circuit using I/O mask signal DQM within the critical path for generating column selection signals is eliminated, and the time from when the clock is supplied until the column selection signal is generated is made as short as possible. On the other hand, to make an I/O mask possible during burst write mode, drive control of the write amplifier is performed based on I/O mask signal DQM. Specifically, activation of the write amplifier is prohibited or allowed in response to the I/O mask signal DQM.

REFERENCES:
patent: 5148396 (1992-09-01), Nakada
patent: 5629899 (1997-05-01), Sato
patent: 5787046 (1998-07-01), Furuyama et al.

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