Memory device performance by delayed power-down

Details Memory device performance by delayed power-down Memory device performance by delayed power-down

1995-11-21

1997-09-16

Nelms, David C.

Static information storage and retrieval

Powering

365227, 365194, 327285, 327288, G11C 700

Patent

active

056687699

ABSTRACT:
The method of this invention prevents transient currents at high-frequency disable cycles and disables DC current paths after a minimum delay time, thereby reducing power dissipation. This invention includes a delay circuit functioning to prevent disablement of DC paths where chip-disable times occur at intervals below a minimum duration. The result is a decrease in the number of undesired voltage drops on internal power buses due to transient currents. The method detects external chip-disable pulses that occur before a minimum time duration, then prevents those pulses from powering down internal direct-current paths. At the same time, the output driver high impedance functionality of the chip-disable signal is preserved.

REFERENCES:
patent: 5033026 (1991-07-01), Tsujimoto

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