Static information storage and retrieval – Addressing – Byte or page addressing
Reexamination Certificate
2005-11-15
2005-11-15
Phung, Anh (Department: 2824)
Static information storage and retrieval
Addressing
Byte or page addressing
C365S230020, C365S230030, C365S185120
Reexamination Certificate
active
06965540
ABSTRACT:
A memory device includes 4 memory banks each of which includes first and second arrays of memory cells. A mode register is programmed with a bit that selects a high-power, large-page operating mode or a low-power, small-page operating mode. In the high-power mode, a row decoder is coupled to the row lines in both the first and second arrays. In the low-power mode, the row decoder is coupled to the row lines in only one of the arrays as determined by the state of an array select signal. The array select signal corresponds to the most significant bit of the column address, but it is applied to the memory device at the time the row address is applied to the memory device. Sense amplifiers coupled to the first and second arrays may also be selectively enabled when the row lines for the corresponding array are coupled to the row decoder.
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Farrell Todd D.
Schaefer Scott E.
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