Memory device, memory system and method of operating such

Details Memory device, memory system and method of operating such Memory device, memory system and method of operating such

2007-04-16

2010-02-16

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189050, C365S236000

Reexamination Certificate

active

07663964

ABSTRACT:
A memory device including a memory cell array; an input circuit providing drive signals to the memory cell array dependent on externally received command data; an output buffer buffering data read out from the memory cell array; and a timer driving the output buffer such that the buffered data are provided at an output after an adjustable time interval has elapsed, the adjustable time interval beginning with the provision of the drive signals.

REFERENCES:
patent: 6166990 (2000-12-01), Ooishi et al.
patent: 6542416 (2003-04-01), Hampel et al.
patent: 6643193 (2003-11-01), Yamaki et al.
patent: 6665222 (2003-12-01), Wright et al.
patent: 2005/0081085 (2005-04-01), Ellis et al.
JEDEC Standard, Double Data Rate (DDR) SDRAM Specification, JESD79-D, (Revision of JESD79C), JEDEC Solid State Technology Association, 2500 Wilson Boulevard, Arlington, VA 22201-3834, Jan. 2004, pp. 1, 5, 8 and 9.

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