Memory device, memory controller and memory system having...

Details Memory device, memory controller and memory system having... Memory device, memory controller and memory system having...

2007-02-20

2007-02-20

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S233100, C365S230050

Reexamination Certificate

active

10954869

ABSTRACT:
One embodiment of the present invention provides to a memory device adapted to receive data according to a write clock signal and to output data according to a read clock signal, comprising a clock port configured to output the read clock signal and to receive the write clock signal and a serial bidirectional driver configured to output the read clock signal via the clock port and to receive the write clock signal via the clock port simultaneously.

REFERENCES:
patent: 6898726 (2005-05-01), Lee
patent: 6941484 (2005-09-01), To et al.
patent: 2002/0129215 (2002-09-01), Yoo et al.
patent: 2003/0026162 (2003-02-01), Matsui
patent: 2003/0206475 (2003-11-01), Duh et al.
Matthew Haycock and Randy Mooney, “3.2GHz 6.4Gb/s per Wire Signaling in 0.18μm CMOS”, 2001 IEEE International Solid-State Circuits Conference, pp. 62, 63 and 430.
Joseph Kennedy et al., “A 2Gb/s Point-to-Point Heterogeneous Voltage Capable DRAM Interface for Capacity-Scalable Memory Subsytems”, 2004 IEEE International Solid-State Circuits Conference, Session 11.8.
Jin-Hyun Kim et al., “A 4 Gb/s/pin 4-Level Simutaneous Bidirectional IO using a 500MHz Clock for High-Speed Memory”, 2004 IEEE International Solid-State Circuits Conference, Session 13.9.

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