Memory device including memories having different capacities

Details Memory device including memories having different capacities Memory device including memories having different capacities

1987-05-06

1989-02-28

Hecker, Stuart N.

Static information storage and retrieval

Addressing

364900, G11C 800

Patent

active

048092347

ABSTRACT:
A memory device includes a plurality of memory arrays, each having a plurality of memory elements, placed in a memory address space, a memory array selecting device responsive to the address information for designating a given address in the memory address space to select one memory array from the plurality of memory arrays, an address generating device for generating the row and column addresses of the selected memory array, and a setting device for setting memory element information corresponding to the capacity of memory elements in each of the memory arrays, the memory array selecting device responsive to the address information and the memory element information for decoding corresponding to the memory capacity to select the desired memory array, and the address generating device responsive to the address information to generate the row and column addresses of the memory array consisting of memory elements of the maximum capacity.

REFERENCES:
patent: 4400794 (1983-08-01), Koos
patent: 4468731 (1984-08-01), Johnson et al.
patent: 4545010 (1985-10-01), Salas et al.
patent: 4566082 (1986-01-01), Anderson
patent: 4675808 (1987-06-01), Grinn et al.
'85 Mitsubishi Semiconductor Data Book, (1C Memory vol.), Applications--64K-Bit Dynamic RAM Designs, Mitsubishi Electric Semiconductor Data Editorial Committee.

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