Memory device including a column decoder for decoding five colum

Details Memory device including a column decoder for decoding five colum Memory device including a column decoder for decoding five colum

1998-02-05

1999-10-26

Mai, Son

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523003, G11C 800

Patent

active

059739860

ABSTRACT:
A memory device including a plurality of memory cells, a plurality of bit lines, a plurality of bit line sense amplifiers, a plurality of column port gates, and a column decoder connected to a multiple of five column port gates. Each of the bit line sense amplifiers is connected to at least one of the bit lines and to at least one of the memory cells. Each of the column port gates is connected to at least one of the bit line sense amplifiers. The column decoder provides signals to the column port gates to which it is connected to select corresponding bit lines connected to the column port gates.

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patent: 5315548 (1994-05-01), Ooishi et al.
patent: 5386387 (1995-01-01), Tanizaki
patent: 5566128 (1996-10-01), Magome
patent: 5610865 (1997-03-01), Shin et al.
Multi-Logic Level DRAM: A Differential Approach; Jeff Gilbert et al.; Worldwide Web.

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