Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2003-07-11
2004-12-28
Phung, Anh (Department: 2824)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S201000, C365S230060
Reexamination Certificate
active
06836445
ABSTRACT:
FIELD OF INVENTION
The present invention relates to a semiconductor memory device; and, more particularly, to a semiconductor memory device having enhance ability of a test for finding fault of a semiconductor memory device.
DESCRIPTION OF PRIOR ART
A semiconductor memory device includes a plurality of memory cells. If any cell in the semiconductor memory device is operated out of order, the semiconductor memory device is useless. After the semiconductor memory device is fabricated, there is needed a test process for finding a defective cell in the semiconductor memory device.
Typically, the semiconductor memory device has an additional area for a test circuit which can test all cells in the semiconductor memory device on high speed. However, according to increasing integration of the semiconductor memory device, there is needed a lot of time and effort for testing cells of the semiconductor memory device so as to research and develop the semiconductor memory device.
FIG. 1
is a block diagram showing a conventional semiconductor memory device.
As shown, the memory device includes four banks
100
,
200
,
300
and
400
. Outputs of the four banks are inputted to a data output buffer
500
. The data output buffer
500
outputs a data inputted from the data output buffer
500
into an external circuit through an output pad
500
′ in response to a clock singal.
One bank, e.g.,
100
, includes first and second cell blocks
110
and
150
, each having a plurality of cell arrays and I/O sense amplifiers
130
and
140
for respectively amplifying data outputted from the first and the second cell blocks
110
and
150
to output the amplified data to the data output buffer
500
.
The first cell block
110
has cell arrays
111
to
116
having a plurality of cells and bit line sense amplifiers
117
to
120
for amplifying and outputting data of cells. Also, the structures of the second to the forth banks
200
,
300
, and
400
are the same to that of the first banks
100
, though the second to the forth banks
200
,
300
, and
400
are not shown in the
FIG. 1
in detail for the sake of convenience.
FIG. 2
describes a preferred embodiment of a bit line sense amplifier logic shown in FIG.
1
.
As shown, the bit line sense amplifier
117
includes a bit line sense amplifier
117
d
for sensing and amplifying a gap between voltages of the bit line pair BL and /BL; an equalization logic
117
c
for precharging and equalizing the voltage of the bit line pair BL and /BL; a first connection logic
117
a
for connecting the cell array
111
to one side of the bit line sense amplifier; a second connection logic
117
b
for connecting the cell array
113
to the other side of the bit line sense amplifier; and an output logic
117
e
for outputting the bit line voltage amplified by the bit line sense amplifier
117
d
. Herein, RTO and /S are enable signals which can enable or disable the bit line sense amplifier
117
d
. BISH and BISL are enable signals which can enable or disable the first and the second connection logic
117
a
and
117
b
. Vblp is a bit line voltage which will be precharged. BIEQ is an enable signal which can enable or disable the equalization logic
117
c
. A column selecting signal YI is an enable signal which can enable or disable the output logic
117
e.
Hereinafter, referring to FIG.
1
and
FIG. 2
, the data path in the semiconductor memory device is described in detail.
First, if an address is inputted to the memory device, a word line of a selected cell array in a bank is enabled corresponding to the address. A MOS transistor M
1
connected to the enabled word line WL is turned on so that data stored in a capacitor C
1
is supplied to a bit line pair BL and /BL. Then, the bit line sense amplifier
117
d
senses and amplifies the data signal because the data signal stored in the capacitor C
1
is too weak.
If the column selecting signal YI is enabled, the data signal sensed and amplified by the bit line sense amplifier
117
d
is outputted to a data line pair DB and /DB. The data outputted data of the data line pair DB and /DB is amplified one more time by a DB sense amplifier, e.g., block
130
shown in
FIG. 1
, and, then outputted to the external circuit through the output buffer
500
.
The DB sense amplifier should be needed for amplifying the weaken data because the data line pair DB and /DB is relatively long. Also, a number of the DB sense amplifier is determined by a size of data simultaneously outputted by the column selecting signal YI. Typically, there is one DB sense amplifier on the front of one bank.
Referring to
FIG. 2
that one bit data is outputted to the data line pair DB and /DB by the column selecting signal YI. However, there is recently needed a memory device which can be operated on high speed. Thus, the memory device is designed so that four-bit data is outputted at once to the DB sense amplifier in response to one column selecting signal YI.
The inputted address may be split into a row address and a column address. The row address enables the word line and the column selecting signal YI is generated from the column address.
FIG. 3
is a block diagram showing a conventional test block for testing a synchronous memory device. As shown, one bank, e.g., the first bank
100
, includes the first cell block
110
and the second cell block
150
. For operation on high speed, the bank has the first and the second cell blocks
110
and
150
, and each cell block has a DB sense amplifier and a decoder.
The test block for testing the memory device includes a Y counter
720
for receiving an address AD<
0
> to AD<
9
> from the external circuit and orderly counting it; a first and a second YI decoders
740
and
750
for decoding outputted addresses YA<
0
> to YA<
9
> from the Y counter and outputting the column selecting signal YI to each of the first and the second cell blocks
110
and
150
; DB sense amplifiers
130
and
140
for amplifying an outputted data signal from the first and the second cell blocks
110
and
150
; a test circuit
600
for combining an outputted data signal from the DB sense amplifiers
130
and
140
and performing a test process; and an output buffer
530
for buffering an output signal from the test circuit
600
and outputting it to the external circuit through a pad. Furthermore, the bank has an instruction controller for controlling the Y counter
720
by receiving several instruction signals such as /CS, /CAS, and so on.
FIG. 4
is a timing chart showing a test operation of the test block shown in FIG.
3
.
Hereinafter, referring to
FIG. 3
to
4
, the test operation of the memory device is described in detail.
If the several instruction signals inputted to the instruction controller
710
are correspondent to a test mode, the memory device is operated in the test mode. The Y counter
720
receives column addresses AD<
0
> to AD<
9
> and counts the column addresses AD<
0
> to AD<
9
> by a burst length BL and, outputs the counted column address YA<
0
> to YA<
9
>. The burst length BL is a kind of specifications in the synchronous memory device; and, in detail, means a number of data which is continuously outputted when one address is inputted. For instance, if the burst length is four, the counter
720
counts the received column addresses at four times and, then outputs the counted column address.
The first YI decoder
740
receives the counted addresses YA<
0
> to YA<
9
> outputted from the Y counter
720
and outputs a 8-bit test data by selecting the two YI lines YI<a> and YI<b> in YI lines YI<
0
> to YI<
1023
>. As shown in
FIG. 2
, a data signal which is sensed by the bit line sense amplifier is outputted by a YI line. It is assumed that four bit data is outputted if one YI line is selected.
If the memory device is operated in a 0×16 mode, a four-bit data signal is simultaneously outputted by one YI line. If each two YI lines in the first and second cell blocks
110
and
150
, i.e., total four YI l
Hynix / Semiconductor Inc.
Marshall & Gerstein & Borun LLP
Nguyen Dang T
Phung Anh
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