Memory device having row decoder

Details Memory device having row decoder Memory device having row decoder

2000-07-10

2001-03-06

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C326S105000, C326S106000

Reexamination Certificate

active

06198686

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory device such as a dynamic random access memory (DRAM) having row decoder with a reduced timing margin or a reduced through-current.
2. Description of the Related Art
For memory device, high speed operation is required with the high speed operation of micro processor unit (MPU).
FIG. 18
shows a circuit of a row address system of a prior art memory
10
. N-shaped bending lines in the drawings denote long-distance wiring in a chip.
Row address having A
8
through A
15
bits from external is provided to the data input of a row address register
11
via a buffer gate
12
A for a signal level interface, while a chip selection signal *CS (* denotes that its signal is active when it is low), a row address strobe signal *RAS, a column address strobe signal *CAS, a write enable signal *WE, a clock enable signal CKE and a clock signal CLK, which are from external, are provided via a buffer gate
12
B to a control circuit
13
including a command decoder and generating various control signals. For example, as one of the control signals, a signal AS
1
activated in response to issuance of an activate command is generated.
Meanwhile, a signal propagation delay time of long-distance wiring in a chip depends on the variance of parasitic resistance and parasitic capacity resulting from variance in production processes, variance per chip in power source voltage used, and changes in temperatures. Furthermore, since the distances from the pads on a chip for the row address of A
8
through A
15
to the row address register
11
differ from bit to bit, skews will occur among signals.
FIG. 19
are time charts showing operations of FIG.
18
. In
FIG. 19
, each solid line shows a case where the signal propagation delay time is the mean, each dashed line and each dotted line show cases where the signal propagation delay time is the maximum and the minimum causing from the above-described reasons, respectively.
It is assumed that the row address signal ADRO and the control signal CMD
0
at the outputs of the buffer gates
12
A and
12
B, respectively, change simultaneously at a time T
1
. The front edges of the row address ADR
1
at the data input of the row address register
11
and the control signal AS
1
as a strobe signal near the clock input CK of the row address register
11
delay from the time T
1
as shown in FIG.
19
.
In a case where the signal propagation delay time to the data input of the row address register
11
is the largest and the signal propagation delay time to the clock input CK of the row address register
11
is the smallest, in order to hold row addresses in the row address register
11
without error, it is necessary to delay the control signal AS
1
by a time TD
1
shown in
FIG. 19
in a timing generation circuit
14
to generate a strobe signal AS
2
and to provide it to the clock input CK of the row address register
11
.
Output of the row address register
11
is provided via a complementary signal generation circuit
15
and a predecoder
16
to a word decoder
17
. These complementary signal generation circuit
15
, predecoder
16
and word decoder
17
constitute a row address decoder. The word decoder
17
is formed along one side of one memory block in a memory core block
18
A, and the word decoder
17
is located near one side of a chip. Since the number of output lines of the complementary signal generation circuit
15
is twice as many as that of input lines, the circuit
15
and
16
are formed near the word decoder
17
to decrease the length of many lines. Since a memory core block
18
B is formed to-be symmetrical with the memory core block
18
A and a word decoder in the memory core block
18
B is formed near the opposite side of the chip, the row address register
11
is formed near the middle point between the memory core blocks
18
A and
18
B.
Therefore, the wiring from the row address register
11
to the complementary signal generation circuit
15
is long.
Memory cells (not shown) in row are coupled to each word line WL shown with dotted line in FIG.
18
and the word lines are connected to the output of the word decoder
17
. Memory cells (not shown) in column are connected to bit lines BL and *BL which are connected to a circuit
19
including a sense amplifier, a precharge circuit and a column gate. Memory cells in a row are selected with an activate word line and contents thereof are read onto bit lines. Since the word decoder
17
is provided with a logic gate circuit for each word lines WL, there is no allowance for arranging other circuits in this circuit area. If there is a skew among the edges of the input signal to the word decoder
17
, an erroneous word line will be selected for a moment.
Therefore, in order to secure the output timing of the word decoder
17
, the timing of the output PDA
0
of the, predecoder
16
at the preceding stage is secured. Namely, a signal S
1
on the same line of the control signal AS
1
is delayed at a timing generation circuit
20
to generate a strobe signal S
2
, and this signal is provided to the predecoder
16
.
The output ADR
2
of the row address register
11
, the input ADR
3
of the complementary signal generation circuit
15
, the output CADR
0
of the circuit
15
and the input CADR
1
of the predecoder
16
are delayed one after another as shown in FIG.
19
.
As in the above description, in a case where the signal propagation delay time to the data input of the predecoder
16
is the largest and the signal propagation delay time to the strobe signal input of the predecoder
16
is the smallest, in order to prevent the output signal PDA
0
of the predecoder
16
from a skew, it is necessary to delay the signal S
1
by a time TD
2
shown in
FIG. 19
in a timing generation circuit
20
to generate a strobe signal S
2
and to provide it to the strobe signal input of the predecoder
16
. The output PDA
0
of the predecoder
16
changes on the front edge of the strobe signal S
2
as shown in FIG.
19
.
However, since the time from a change in the row address signal of A
8
through A
15
till a change in the signal on a selected word line WL becomes long due to the delay times TD
1
and TD
2
at the timing generation circuits
14
and
20
, the high speed operation of the memory
10
is hindered.
On the other hand, low power consumption is required in memory devices for uses in portable electronic devices.
In a synchronous DRAM, since it is provided with a plurality of banks which enables a high speed access with switching over banks in every clock pulse and operating the banks in parallel. To enable this parallel operation, latch circuits are connected, for respective word lines, at the output stage in word decoder circuits to which signals obtained by predecoding the row addresses are provided.
FIG. 20
shows a circuit for one word line, which is a part of a word decoder.
A word decoding circuit
60
is a NAND gate in which NMOS transistors
61
and
62
are connected in series, and predecoded signals SS
1
and SS
2
are provided to gate electrodes of the NMOS transistors
61
and
62
, respectively. To select a word line WL, the predecoded signals SS
1
and SS
2
are made high, whereby the signal SS
3
goes low. The signal SS
3
is hold in a latch circuit
70
, and a signal SS
4
generated with inverting the signal SS
3
is outputted from the latch circuit
70
.
In the latch circuit
70
, inverters
71
and
72
are connected in ring-shaped, and an NMOS transistor
73
for setting is connected between the output of the inverter
72
and the ground potential, and an NMOS transistor
74
for resetting is connected between the output of the inverter
71
. and the ground potential.
The drive capacity of the signal SS
4
is amplified by a driver
80
to drive the word line WL.
Since a memory device is activated in units of a block in order to reduce power consumption, a word reset signal WRST is commonly provided to all the latch circuits in an activated memory block when an access is finished, whereby the NM

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