Static information storage and retrieval – Read only systems – Magnetic
Reexamination Certificate
2001-11-26
2002-11-19
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read only systems
Magnetic
C365S096000, C365S100000, C365S046000
Reexamination Certificate
active
06483734
ABSTRACT:
TECHNICAL FIELD
The technical field is memory devices for storing data. More particularly, the technical field is memory devices having memory cells capable of storing four different bits.
BACKGROUND
Memory devices are utilized in consumer electronic products to store data such as instructions utilized by the products. Nonvolatile memory devices are desirable because they do not require power to store data. Therefore, data stored in nonvolatile memory devices is preserved when a power supply is exhausted or disconnected from the memory device. Consumers also prefer products of small volume and low cost, and the requirements of nonvolatility, high density, and low cost are primary driving factors in the design of memory devices. Low power consumption is also desirable because smaller power sources can be used, reducing the size of consumer electronic products.
Nonvolatile memory devices typically have one time programmable (OTP) or reprogrammable memory cells. A reprogrammable, or “re-writeable” memory cell can be switched among binary states. An OTP, or “write-once” memory cell's state is permanent once the cell is programmed. OTP memory devices can generally be classified as one of fuse, anti-fuse, charge storage, or mask read only memory (mask ROM).
A fuse memory cell is programmed by applying a voltage across the cell so that the cell is “blown” during programming. The binary state of fuse memory cells can be detected as the resistance of the cell measured during a read process. Conventional fuse memory devices have a low array density because the contact regions required for each fuse element occupy a large area of the substrate. Conventional fuse memory cells also often include an isolation element such as a diode or transistor, which further increases cell size. Isolation diodes and transistors have limited current capability, and may be damaged by the write currents required to program the fuse memory cells. In addition, the isolation diodes and transistors are typically active silicon-based elements, which are most readily formed on a silicon crystal substrate. Isolation elements of this type may preclude stacking of multiple layers of fuse OTP arrays, decreasing possible device capacity. Silicon-based isolation elements such as micro-crystalline and amorphous diodes and transistors may enable stacking, but increase complexity and cost of fabrication.
Conventional anti-fuse memory cells typically include a metal-dielectric-metal stack. Conventional anti-fuse memory cells are programmed by applying a write potential across the cells. The write potential triggers the anti-fuse and reduces the resistance of a programmed memory cell. Conventional anti-fuse memory cells suffer many of the same disadvantages as fuse/transistor cells. For example, conventional anti-fuse memory cells may require silicon-based isolation elements, which decrease array density.
A common conventional charge storage memory is EPROM. EPROM memory utilizes Fowler-Nordheim tunneling to transfer charge from a substrate to a floating gate in the memory cell. EPROM memories require a large write voltage, and the write speed in EPROM devices is limited by tunneling current density.
Mask ROM memories are programmed at the time of fabrication, rather than at the user level (“field programming”). Therefore, each batch of mask ROM devices is application-specific. As in most manufacturing processes, cost savings are realized with increased volume. Therefore, in order for mask ROM production to be cost-effective, there must be a large demand for an application-specific memory. The requirement for large-scale processing renders mask ROM too costly for many applications.
FIG. 1
illustrates a conventional MRAM memory array
10
having resistive memory cells
12
located at cross points of word lines
14
and bit lines
16
. The word lines
14
extend horizontally along rows of the memory array
10
, and the bit lines
16
extend vertically along columns of the memory array
10
. Each memory cell
12
is capable of storing the binary states of “1” and “0”
FIG. 2
illustrates a conventional MRAM memory cell
12
. The memory cell
12
includes a pinned layer
24
and a free layer
18
. The pinned layer
24
has a magnetization that has a fixed orientation, illustrated by the arrow
26
. The magnetization of the free layer
18
, illustrated by the bi-directional arrow
28
, can be oriented in either of two directions along an “easy axis” of the free layer
18
. If the magnetizations of the free layer
18
and the pinned layer
24
are in the same direction, the orientation of the memory cell
12
is “parallel.” If the magnetizations are in opposite directions, the orientation is “anti-parallel.” The two orientations correspond to the binary states of “1” and “0,” respectively.
The free layer
18
and the pinned layer
24
are separated by an insulating tunnel barrier layer
20
. The insulating tunnel barrier layer
20
allows quantum mechanical tunneling to occur between the free layer
18
and the pinned layer
24
. The tunneling is electron spin dependent, making the resistance of the memory cell
12
a function of the relative orientations of the magnetizations of the free layer
18
and the pinned layer
24
. The resistance of the memory cell
12
may have a “low” value of R−&Dgr;/2 if the orientation is parallel, and a “high” value of R+&Dgr;/2 if the orientation is anti-parallel.
Each memory cell
12
in the memory array
10
can have its binary state changed by a write operation. Write currents Ix and Iy supplied to the word line
14
and the bit line
16
crossing at a selected memory cell
12
switch the magnetization of the free layer
18
between parallel and anti-parallel with the pinned layer
24
. The current Iy passing through the bit line
16
results in the magnetic field Hx, and the current Ix passing through the word line
14
results in the magnetic field Hy. The fields Hx and Hy combine to switch the magnetic orientation of the memory cell
12
from parallel to anti-parallel. A current−Iy can be applied with the current Ix to switch the memory cell
12
back to parallel. In order to switch the state of the memory cell
12
from parallel to anti-parallel, and vice versa, the combined field created by Hx and +/−Hy exceed a critical switching field Hc of the memory cell
12
. The change in resistance due to the changing memory cell magnetization is readable to determine the binary state of the memory cell
12
.
While MRAM memory provides for stable storage of data and reprogrammability, only two states can be stored in conventional MRAMs. The limitation of data storage to two bit states per MRAM memory cell limits the data storage density of conventional MRAM memory arrays.
A need therefore exists for a memory device having memory cells capable of high data storage density arrangement and relatively low cost.
SUMMARY
According to a first aspect, a memory array includes a plurality of memory cells located at the intersections of word and bit lines. The memory cells each have two storage elements in series. One storage element is a re-writeable element, and the other is a write-once element. The re-writeable element is programmable between a high resistance state and a low resistance state. The write-once element can be an anti-fuse element that is also programmable from a high resistance state to a low resistance state, or a fuse element that is programmable from a low resistance state to a high resistance state.
According to the first aspect, the two possible states for the re-writeable element and the two possible states for the write-once element allow the memory cells to occupy four different states, and therefore store four bits of data.
Also according to the first aspect, the memory cells are smaller than conventional memory cells having diode/transistor isolation elements. This aspect further increases array density.
Also according to the first aspect, the memory device can operate at a low programming voltage by using a relatively thin tunnel barrier in the
Sharma Manish
Tran Lung T.
Hewlett -Packard Company
Hoang Huan
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