Memory device having a plurality of bitlines between adjacent co

Details Memory device having a plurality of bitlines between adjacent co Memory device having a plurality of bitlines between adjacent co

1996-05-17

1998-01-13

Nelms, David C.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365 64, 36518908, 36523003, G11C 800

Patent

active

057086206

ABSTRACT:
A memory device of the present invention includes a plurality of bitlines and main wordlines formed in first and second directions, respectively, to form a matrix, and a plurality of memory cells coupled to each bitline. A first decoder decodes first address signals and provides first decoded signals to the plurality of main wordlines. A second decoder decodes second address signals and provides second decoded signals. The memory device also includes n-th number of groups of drivers, and each group has a plurality of sub-drivers formed in a third direction to receive a corresponding second decoded signal. Each sub-driver has a plurality of selection lines coupled to corresponding memory cells, and a plurality of sense amplifiers is coupled to said plurality of bitlines, wherein more than two bitlines are formed between adjacent groups of drivers.

REFERENCES:
patent: 5107459 (1992-04-01), Chu et al.
patent: 5172335 (1992-12-01), Sasaki et al.
patent: 5416748 (1995-05-01), Fujita
patent: 5506816 (1996-04-01), Hirose et al.

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