Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Utility Patent
1999-05-26
2001-01-02
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S194000, C365S233500
Utility Patent
active
06169702
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of integrated circuits, and, more particularly, to a memory device.
BACKGROUND OF THE INVENTION
In asynchronous static random access memory (SRAM) devices, no external clock signals are provided. This requires an internally generated clock signal to provide the timing signals for the memory device to operate. The clock signals are produced when an input to the memory device, i.e., an address signal, transitions. This implies that some externally connected device, such as a microprocessor, commands the memory device to perform either a read or a write operation based on new input information.
However, an SRAM device has another input known as a chip select, which places the memory device either in an active select mode or in an inactive deselect mode. The chip select function has long been used in memory devices to disable a memory device to reduce power consumption. Consequently, address on-chip receivers (OCRs) are not responsive to external address signals when the memory device is in the deselect mode.
When an address input signal has been provided to an address input, the deselected address OCR can not respond until it receives the chip select pulse. The chip select pulse is first applied to a chip select input, which is received by the chip select OCR. The chip select OCR then relays the chip select pulse to the address OCR. Unfortunately, the time required for the chip select OCR to relay the chip select pulse to the address OCR introduces an additional time delay when the SRAM comes out of the deselect mode into the select mode.
An external controller, such as a microprocessor, provides the address signal and the chip select pulse to the memory device placing the memory device in the select mode. Referring to
FIG. 1
, a chip select pulse applied to the chip select input or pad
20
of an SRAM
18
is received by the chip select OCR
22
. The chip select OCR
22
then relays the chip select pulse to the address OCR
24
. As explained above, the additional time delay from the chip select OCR
22
to the time the address OCR
24
is enabled is added to the chip select access time.
During this additional time delay, an address signal has already been provided to the address input or pad
26
the same time the chip select pulse was applied to the chip select input. When the memory device
18
is in the select mode, there is no delay because the chip select pulse has already enabled the address OCR
24
so that it immediately responds to an address input signal. In other words, this additional chip select access time delay is only experienced when the SRAM
18
transitions from the deselect mode to the select mode.
The additional time delay introduced by the chip select OCR
22
is propagated throughout the remaining signal paths connected to the address OCR
24
. As shown in
FIG. 1
, the output of the address OCR
24
is connected to an address decoder
28
via an address delay circuit
30
, and to an address transition detect (ATD) circuit
32
. Because of the unavoidable time delay in responding to the chip select pulse, a longer access time is required when the memory device
18
is coming out of the deselect mode to the select mode. An approach to avoid the extended access time has been to keep the address OCRs
24
on during the deselect mode and incur the resulting additional power loss.
SUMMARY OF THE INVENTION
In view of the foregoing background, it is therefore an object of the present invention to reduce the chip select access time for an SRAM device, as when transitioning the SRAM device from a deselect mode to a select mode.
It is another object of the invention to improve the chip select access time for an SRAM device without incurring an additional power loss.
It is yet another object of the invention to provide a method for reducing a chip select access time when transitioning an SRAM device from a deselect mode to a select mode.
These and other objects, features and advantages in accordance with the present invention are provided by a memory device having a plurality of address on-chip receivers (OCRs) for receiving an address signal, an address decoder connected to the address OCRs, and a plurality of first delay circuits, each of which is respectively coupled between the address OCRs and the address decoder, and a plurality of chip select bypass circuits. Each chip select bypass circuit is respectively coupled to one of the plurality of first delay circuits for initially reducing a delay therein responsive to a control signal.
Each chip select bypass circuit includes a second delay circuit having a delay less than the first delay circuit, and a disable circuit. The disable circuit disables the first delay circuit and selectively couples the second delay circuit in place of the first delay circuit responsive to the control signal. The control signal is generated by a chip select OCR responsive to a chip select pulse.
The first delay circuit includes a plurality of inverter delay stages, and the second delay circuit includes at least one inverter delay stage. Each delay stage includes a pair of series connected n channel metal oxide semiconductor (NMOS) transistors coupled to a first voltage reference, and a pair of series connected p channel metal oxide semiconductor (PMOS) transistors coupled to a second voltage reference. The NMOS and PMOS transistors are coupled together in series. The chip select bypass circuit disables at least one of the plurality of inverter delay stages in the first delay circuit responsive to the control signal.
Since the time delays provided by the first delay circuits are for synchronizing control lines, data lines and selected address lines with the bit line precharge circuits, they are not necessary during a chip select access. Therefore, to speed-up the chip select access time for placing the memory device from a deselect mode to a select mode, the first delay circuits are bypassed via the second delay circuits having a shorter delay path.
Advantageously, the time delay between the address access (normal mode) and a chip select access (select mode) are balanced so that the propagation of the address signal is nearly identical with propagation of other corresponding signals within the memory device. In other words, the time delay introduced by transitioning the memory device from a deselect mode to a select mode is set equal to the time delay of initially receiving the address signal and propagating this signal through the memory device.
The shorter delay path provided by the chip select bypass circuit improves the chip select access time without incurring any additional power consumption, e.g., such as leaving the address OCRs in an enabled mode when the remainder of the memory device is in a deselect mode. When the memory device is included in an electronic device that operates from a battery powered source or is included in an electronic device which has limited ability to generate power, such as a satellite, for example, operation of the electronic device is prolonged when power is conserved. The memory device is a static random access memory (SRAM), which may operate asynchronously or synchronously.
Another aspect of the invention relates to a method for accessing a memory device including a plurality of address on-chip receivers (OCRs) for receiving an address signal; an address decoder connected to the address OCRs; and respective delay circuits connected between the address OCRs and the address decoder. The method includes the step of initially reducing a delay of the delay circuits responsive to a control signal. The method also includes the step of generating the control signal responsive to a chip select pulse.
Each delay circuit includes a first group of delay stages and a second group of delay stages, wherein the second group of delay stages has a delay less than the first group of delay stages. The step of initially reducing the delay of the delay circuits includes selectively coupling the second group of delay stages in place of the first group o
Doyle Scott
Hoang Tri Minh
Lawson David
Zien Livia
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Hoang Huan
Lockheed Martin Corporation
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