Memory device for synchronously reading and writing data

Details Memory device for synchronously reading and writing data Memory device for synchronously reading and writing data

1995-11-22

1997-08-26

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

36518905, G11C 700

Patent

active

056616937

ABSTRACT:
A synchronous memory device is provided in which the cycle time is shorter than conventional memory devices. For example, by providing an output latch in a sense amplifier on a bit line, the time period from input of a clock signal to latching data in the output latch is shortened. In case of plural bit lines, a selector for selecting data in a plural output latch and a latch for latching a sense amplifier selection are provided.

REFERENCES:
patent: 4928265 (1990-05-01), Higuchi
patent: 5222047 (1993-06-01), Matsuda
patent: 5258951 (1993-11-01), Yu
patent: 5343428 (1994-08-01), Pilo
patent: 5455795 (1995-10-01), Nakao

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